The present invention relates to an operation of a nonvolatile memory device and, more particularly, to a method of programming a nonvolatile memory device, which can reduce an interference phenomenon by storing different numbers of bits in neighboring memory cells.
A NAND flash memory device, which is one of the well-known nonvolatile memory devices, includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines arranged along rows, a plurality of bit lines arranged along columns, and a plurality of cell strings, each corresponding to a respective bit line.
A row decoder, connected to a string select line, word lines, and a common source line, is disposed on one side of the memory cell array. A page buffer connected to the bit lines, is disposed on the other side of the memory cell array.
Recently, in order to further increase the level of integration of a flash memory device, active research has been performed on multi-bit cells that are able of storing plural data in one memory cell. This type of the memory cell is called a multi-level cell (hereinafter referred to as an ‘MLC’). A memory cell of a single bit corresponding to the MLC is called a single level cell (hereinafter referred to as an ‘SLC’).
The MLC has wider threshold voltage distributions as it can store an increased number of bits. Further, the MLC experiences an interference phenomenon in which, while a program is performed, the threshold voltage of neighboring memory cells is changed undesirably.